1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display capable of diagnosing abnormal driving states of systems and liquid crystal display panels.
2. Description of the Related Art
Generally, due to advantageous characteristics including small device dimensions and low power consumption, liquid crystal displays (LCDs) have been employed in notebook PCs, office automation equipment, audio/video equipment, etc. Particularly, active matrix liquid crystal displays using thin film transistors (TFTs) as switching devices may be suitable for displaying images dynamically.
FIG. 1 illustrates a schematic block diagram of a conventional LCD.
As shown in FIG. 1, an interface 10 receives data (e.g., RGB data) and control signals (e.g., an input clock signal, a horizontal synchronizing signal, a vertical synchronizing signal, and a data enable signal) inputted from a driving system such as a personal computer (not shown) and applies the data and control signals to a timing controller 12. A low voltage differential signal (LVDS) interface and a transistor transistor logic (TTL) interface are typically used in transmission of data and control signals from the driving system. The interface 10 and the timing controller 12 are usually integrated into a single chip.
The timing controller 12 uses the control signal inputted via the interface 10 to produce control signals suitable for driving a data driver 18 consisting of a plurality of data driver ICs (not shown) and a gate driver 20 consisting of a plurality of gate driver ICs (not shown). The timing controller 12 transfers the data signals from the interface 10 to the data driver 18.
A reference voltage generator 16 includes a digital-to-analog converter (DAC) and generates reference voltages used by the data driver 18. The reference voltages are established by a manufacturer on the basis of a transmissivity-to-voltage characteristic of the liquid crystal display panel. The data driver 18 selects reference voltages from input data in response to control signals from the timing controller 12 and applies the selected reference voltage to the liquid crystal display panel 2, thereby controlling a rotation angle of the liquid crystal. The gate driver 20 turns the thin film transistors (TFTs) arranged on the liquid crystal panel 2 on and off in response to the control signals inputted from the timing controller 12, and allows the analog image signals from the data driver 18 to be applied to each pixel connected to each TFT. A power voltage generator 14 supplies a driving voltage to each element, and generates a common electrode voltage of the liquid crystal display panel 2.
FIG. 2 illustrates a schematic block diagram showing a configuration of the timing controller in FIG. 1.
As shown in FIG. 2, the timing controller 12 includes a control signal generator 22 and a data signal generator 24. The timing controller 12 receives horizontal synchronizing signals, vertical synchronizing signals, data enable signals, clock and data (e.g., R,G,B data) signals. The vertical synchronizing signal represents a time required for displaying one frame field. The horizontal synchronizing signal represents a time required for displaying one line of the field. Thus, the horizontal synchronizing signal includes pulses corresponding to the number of pixels included in one line. The data enable signal represents a time required for supplying the pixel with a data.
The data signal generator 24 receives bits of data (e.g., R,G,B data) from the interface 10. The data signal generator 24 rearranges the data so that predetermined bits of data can be supplied to the data driver 18. The control signal generator 22 receives the horizontal synchronizing signal, the vertical synchronizing signal, the data enable signal and the clock signal from the interface 10, generates various control signals, and applies the various control signals to the data driver 18 and the gate driver 20.
Control signals required by the data driver 18 and the gate driver 20 will be described below. Herein, commonly used control signals, except for specially required signals, will only be described.
Control signals required by the data driver 18 include source sampling clock (SSC), source output enable (SOE), source start pulse (SSP), liquid crystal polarity reverse (POL) signals, etc. The SSC signal is used as a sampling clock signal for latching data in the data driver 18. The SSC signal determines a drive frequency of the data drive IC included in the data driver 18. The SOE signal allows data latched by the SSC signal to be transferred to the liquid crystal display panel 2. The SSP signal determines the initiation of a latch or sampling of the data during one horizontal synchronous period. The POL signal determines the polarity of the liquid crystal for the purpose of driving the liquid crystal display according to an inversion driving method.
Control signals required by the gate driver 20 include gate shift clock (GSC), gate output enable (GOE), gate start pulse (GSP) signals, etc. The GSC signal determines the on/off time of the gate of the TFT. The GOE signal controls an output of the gate driver 20. The GSP signal determines the first drive line of a field in one vertical synchronizing signal.
Control signals inputted to the data driver 18 and the gate driver 20 are generated from the timing controller 12 in response to control signals inputted from the interface 10. Thus, if any control signal is not inputted from the interface 10, then the timing controller 12 cannot generate any control signal. If, in conventional LCDs, control signals are not inputted from the interface 10 upon application of power, a picture cannot be displayed on the liquid crystal display panel.
Moreover, when conventional systems and/or liquid crystal display modules are abnormally driven to display an abnormal picture on the liquid crystal display panel, it is impossible to detect the cause of the abnormal operation.